Currently, SSR flyback converter is the most commonly used circuit in terms of off-line AC-DC converter circuit with intermediate output power.
FIG. 1 illustrates a system schematic of a typical SSR offline flyback AC-DC converter circuit. As shown in FIG. 1, the converter circuit includes an off-line AC-DC controller circuit 1 and a peripheral circuit. The offline AC-DC controller circuit 1 includes an overvoltage detection module 10, a current limiting module 11, a PWM comparator 12, and a switch control module 13.
Referring to FIG. 1, the overvoltage detection module 10 includes a comparator A1. The positive input terminal of the comparator A1 is coupled to a power source terminal VDD. The negative input terminal of the comparator A1 is coupled to an internal reference voltage VREF1. The current limiting module 11 includes a comparator A2. The positive input terminal of the comparator A2 is coupled to a current sampling terminal CS. The negative input terminal of the comparator A1 is coupled to an internal reference voltage VREF2. The PWM comparator, or PWM module 12, includes a comparator A3. The positive input terminal of the comparator A3 is coupled to the current sampling terminal CS. The negative input terminal of the comparator A1 is coupled to a feedback terminal FB. The input of the switch control module 13 is coupled to an output terminal of the comparators A1 to A3. The output of the switch control module 13 is coupled to a gate driven terminal GATE. The gate driven terminal VDD of the controller circuit 1 is coupled to a negative terminal of the external freewheeling diode D6 and an anode plate of the capacitor C3. The current sampling terminal CS of the controller circuit 1 is coupled to the source of the external power transistor M1 and a terminal of the sampling resistor R1. The gate driven terminal GATE of the controller circuit 1 is coupled to the gate of the external power transistor M1.
In the foregoing SSR offline flyback AC-DC converter system, the overvoltage detection for the output voltage Vo is performed by detecting whether the VDD voltage is overvoltage. However, for the same output voltage, when the load varies, there will be a considerable variation in VDD voltage. Thus, the threshold for overvoltage detection may vary significantly as the load varies if the overvoltage detection for the output voltage Vo is performed by detecting VDD voltage.
Accordingly, an SSR offline flyback AC-DC converter circuit as illustrated in FIG. 2 may be adopted. In the converter circuit shown in FIG. 2, an anti-phase terminal of an auxiliary winding N3, after the division by resistors R2/R3, is then coupled to an overvoltage detection terminal OVP of the controller circuit 1, acting as a sample point for overvoltage detection. The relation between the anti-phase voltage V3 of the auxiliary winding N3 and the anti-phase voltage V2 of the secondary winding N2 states as follows:
                                          V            ⁢                                                  ⁢            3                                V            ⁢                                                  ⁢            2                          =                              n            ⁢                                                  ⁢            3                                n            ⁢                                                  ⁢            2                                              (        1        )            
where n3 is the number of turns of the auxiliary winding N3 and n2 is the number of turns of the secondary winding N2.
In addition, when the power transistor M1 is in cut-off state and the current through the secondary and the auxiliary windings continues to flow, the relation between the voltage V3 and the output voltage Vo is expressed as follows:
                              V          ⁢                                          ⁢          3                =                                            n              ⁢                                                          ⁢              3                                      n              ⁢                                                          ⁢              2                                ⁢                      (                          Vo              -                              V                                                                                          ⁢                                      FD                    ⁢                                                                                  ⁢                    5                                                                        )                                              (        2        )            
where VFD5 denotes a forward voltage drop across the diode D5.
At this point, the voltage at the OVP terminal is as follows:
                                                        R              ⁢                                                          ⁢              3                                                      R                ⁢                                                                  ⁢                2                            +                              R                ⁢                                                                  ⁢                3                                              ·                                    n              ⁢                                                          ⁢              3                                      n              ⁢                                                          ⁢              2                                      ⁢                  (                      Vo            +                          V                              FD                ⁢                                                                  ⁢                5                                              )                                    (        3        )            
where R2 and R3 denote resistance of the resistor R2 and the resistor R3.
As can be seen from equation (3), the voltage at the OVP terminal is in linear relation with Vo, which may precisely reflect whether there is overvoltage in the voltage Vo. Thus, the defects that the threshold for overvoltage detection varies with the load, as illustrated in the system shown in FIG. 1, may be overcome by detecting this voltage. However, the shortcoming of the converter circuit shown in FIG. 2 lie in that the controller circuit 1 requires an additional OVP terminal for voltage input.